77 research outputs found

    Synthesis of new simplified hemiasterlin derivatives with α,ÎČ-unsaturated carbonyl moiety.

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    International audienceIn this Letter, we report a convenient and efficient method for the synthesis of new simplified derivatives of hemiasterlin in which the α,α-dimethylbenzylic moiety A is replaced by α,ÎČ-unsaturated aryl groups as Michael acceptor. Most of these derivatives have a strong cytotoxic activity on three human tumor cell lines (KB, Hep-G2 and MCF7). Analogs 17b and 17f showed a high cytotoxicity against KB and Hep-G2 cancer cell lines comparable to paclitaxel and ellipticine

    Synthesis of new bioisosteric hemiasterlin analogues with extremely high cytotoxicity

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    International audienceIn this article, we report a convenient and efficient method for the synthesis of new simplified derivativesof hemiasterlin in which the α,α-dimethylbenzylic moiety A is replaced by α,ÎČ-unsaturated aryl groupsas Michael acceptor. Most of these derivatives have a strong cytotoxic activity on three human tumorcell lines (KB, Hep-G2 and MCF7). Analogs 17b and 17f showed a high cytotoxicity against KB andHep-G2 cancer cell lines comparable to paclitaxel and ellipticine

    Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

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    Sphere detector (SD) is an effective signal detection approach for the wireless multiple-input multiple-output (MIMO) system since it can achieve near-optimal performance while reducing significant computational complexity. In this work, we proposed a novel SD architecture that is suitable for implementation on the hardware accelerator. We first perform a statistical analysis to examine the distribution of valid paths in the SD search tree. Using the analysis result, we then proposed an enhanced hybrid SD (EHSD) architecture that achieves quasi-ML performance and high throughput with a reasonable cost in hardware. The fine-grained pipeline designs of 4 × 4 and 8 × 8 MIMO system with 16-QAM modulation delivers throughput of 7.04 Gbps and 14.08 Gbps on the Xilinx Virtex Ultrascale+ FPGA, respectively
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